The present invention relates, ir general, to the field of integrated circuit semiconductor technology low-dropout ("LDO") voltage regulators. More particularly, the present invention relates to a current efficient LDO voltage regulator incorporating a transient response boost circuit which may be added to selectively apply current to a slew-rate limited node and yet requires no standby current during zero output current load conditions of the LDO voltage regulator.
Low-dropout voltage regulators are typically integrated circuits designed to provide generally fixed output voltages over varying loads with minimal voltage dropout over a relatively wide operating temperature range. They are oftentimes intended for use in portable, battery powered applications such as laptop computers, pagers cellular phones and the like. As a consequence, standby and quiescent current flow are major concerns in their design and some LDO voltage regulators incorporate a separate enable terminal to switch the device into a standby mode of operation to minimize power consumption when the associated device is disabled.
It has been observed that the transient response of an LDO voltage regulator to a full range load current step exhibits an output voltage "glitch". In a low quiescent current operational environment, the characteristics of this glitch are observed to be dominated by a slew-rate limited node defined by the relatively large gate terminal of the LDO voltage regulator series-connected power pass transistor, which, in certain applications, is generally a P-type metal oxide semiconductor ("PMOS") field effect transistor ("FET").
It is known that this undesired effect may be at least somewhat offset by adding more current to this node so as to charge and to discharge the associated capacitance of the gate. However, such a technique is generally not feasible in those typical applications in which low quiescent current flow is either necessary or desired due to the fact that the current boost to the slew-rate limited node of the LDO voltage regulator is not limited solely to "on demand" conditions. As a consequence, known techniques result in circuit designs that either necessitate the toleration of relatively large output glitch specifications or those that require more quiescent current flow than is desired during zero load current conditions.
It has also been observed that the AC requirements of the system are dependent on the load current and that typical implementations provide bias for "worst case" conditions. As a result, the quiescent current is not efficiently utilized and more quiescent current than is necessary may be used under certain conditions.